#define main drill_entry
#include "firmware/固件/drill_target/src/main.c"
#undef main
#include "firmware/固件/drill_target/src/drill_pwm_stage.c"
#include "firmware/固件/drill_target/src/drill_spi_transport.c"
#include "firmware/固件/drill_target/src/drill_safe_gpio.c"
#include <assert.h>
#include <stdio.h>
#include <string.h>
#include <setjmp.h>
RCC_TypeDef rcc;GPIO_TypeDef ga,gb,gf;TIM_TypeDef timer;SPI_TypeDef spi;
static jmp_buf returned;
static unsigned resets;
void host_wait(void){longjmp(returned,1);}
static void pins(GPIO_TypeDef *p){p->ODR=(p->ODR|(p->BSRR&65535u))&~(p->BSRR>>16);p->IDR=p->ODR;p->BSRR=0;}
void host_dsb(void){if(rcc.APB1RSTR1&RCC_APB1RSTR1_SPI2RST)memset(&spi,0,sizeof spi);pins(&ga);pins(&gb);pins(&gf);if(rcc.APB2RSTR&RCC_APB2RSTR_TIM1RST){memset(&timer,0,sizeof timer);++resets;}}
int main(void){
 for(unsigned n=0;n<256;++n){
  memset(&rcc,0,sizeof rcc);memset(&ga,0,sizeof ga);memset(&gb,0,sizeof gb);memset(&gf,0,sizeof gf);
  memset(&timer,0xff,sizeof timer);owned=false;state=UNINITIALIZED;memset(&spi,0xff,sizeof spi);resets=0;drill_debug_pwm_stage_available=99;
  rcc.CR=RCC_CR_HSION|RCC_CR_HSIRDY;rcc.CFGR=RCC_CFGR_SW_HSI|RCC_CFGR_SWS_HSI;
  ga.MODER=gb.MODER=gf.MODER=n*0x01010101u;
  ga.ODR=gb.ODR=gf.ODR=65535;ga.IDR=gb.IDR=gf.IDR=65535;
  if(!setjmp(returned))drill_entry();
  assert(drill_debug_pwm_stage_available==1&&drill_pwm_stage_available());assert(resets==1);assert(drill_debug_spi_available==1&&drill_spi_available());
  assert(timer.CCER==0&&!(timer.CR1&TIM_CR1_CEN)&&!(timer.BDTR&TIM_BDTR_MOE));
  assert((ga.ODR&((1u<<5)|(1u<<7)|(7u<<8)))==0&&!(gb.ODR&3u)&&!(gf.ODR&2u));
  assert(ga.ODR&(1u<<12));assert(timer.CCR1==0&&timer.CCR2==0&&timer.CCR3==0);
 }
 puts("256 REAL MAIN SAFE-BOOT TO STOPPED TIM1 SCENARIOS PASS");
}
