#include "stm32g0xx.h"
#include "display_bus.h"
static bool ready;
static void scl(void*c,bool release){(void)c;GPIOA->BSRR=release?(1u<<6):(1u<<22);}
static void sda(void*c,bool release){(void)c;GPIOA->BSRR=release?(1u<<7):(1u<<23);}
static bool read_scl(void*c){(void)c;return (GPIOA->IDR&(1u<<6))!=0;}
static bool read_sda(void*c){(void)c;return (GPIOA->IDR&(1u<<7))!=0;}
static uint16_t ticks(void*c){(void)c;return (uint16_t)TIM14->CNT;}
static si_bus bus={0,scl,sda,read_scl,read_sda,ticks,SI_ARGUMENT,0,0};
bool display_bus_init(void){
 ready=false;
 /* Dedicated TIM14 timebase; no output channel or IRQ configured.
    Candidate runs only with undivided16MHz CPU/APB reset clock. */
 if(SystemCoreClock!=16000000u||(RCC->CFGR&(RCC_CFGR_HPRE|RCC_CFGR_PPRE))!=0u)return false;
 RCC->IOPENR|=RCC_IOPENR_GPIOAEN; (void)RCC->IOPENR;
 GPIOA->BSRR=(1u<<6)|(1u<<7); /* release before switching pin mode */
 GPIOA->OTYPER|=(1u<<6)|(1u<<7);
 GPIOA->PUPDR&=~((3u<<12)|(3u<<14));
 GPIOA->MODER=(GPIOA->MODER&~((3u<<12)|(3u<<14)))|(1u<<12)|(1u<<14);
 RCC->APBENR2|=RCC_APBENR2_TIM14EN;(void)RCC->APBENR2;
 TIM14->CR1=0;TIM14->DIER=0;TIM14->CCER=0;TIM14->PSC=15;
 TIM14->ARR=65535;TIM14->CNT=0;TIM14->EGR=TIM_EGR_UG;TIM14->SR=0;
 TIM14->CR1=TIM_CR1_CEN;ready=true;return true;
}
bool display_bus_write(void*c,uint8_t a,const uint8_t*b,size_t n){
 (void)c;if(!ready)return false;return si_write(&bus,a,b,n);
}
si_status display_bus_last_status(void){return bus.status;}

bool display_bus_read_register(uint8_t a,uint8_t r,uint8_t*out,size_t n){
 if(!ready){bus.status=SI_ARGUMENT;if(out&&n<=17)for(size_t i=0;i<n;i++)out[i]=0;return false;}
 return si_read_register(&bus,a,r,out,n);
}
