PASS 50 owner initialization, nonmutation, mux preservation, runtime corruption and real-reader abort cases; register model only.
PASS 65713 addressed cases plus wrap/backward, all stage errors, timeouts, partial/STOP/BUSY/ownership checks. Register model only.
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS actual A50 reader + A51 target adapter + async bank end-to-end MMIO simulation
PASS runtime reset/recovery, two diagnostic banks, zero eligible masks; MMIO simulation only
PASS 120 diagnostic runtime scenarios: two scans, 90 GPIO/config/alias faults across three phases, four scheduling/ownership faults, tick wrap, 24 NACK positions.
PASS writer: 18 complete frames, 275 byte/STOP-position hardware errors, 65536 address/control combinations, 27 lengths, collision/cancel/time/config tests; MMIO only
PASS 174 explicit write/read matches with MODE2 fixed bits and wake waits; model only
PASS 174 explicit write/read matches with MODE2 fixed bits and wake waits; model only
PASS 174 explicit write/read matches with MODE2 fixed bits and wake waits; model only
PASS total 500ms initialization deadline with timely individual transactions
PASS 528 dark initialization scenarios: normal/wrap, 174 write NACKs, 174 read NACKs, 174 mismatches, poll gap, MODE2 fixed bits, terminal abort, total deadline.
PASS qualified-fixture 61-channel image, 174 readbacks, unused channels zero, post-commit revocation; no physical output
PASS qualified-fixture 61-channel image, 174 readbacks, unused channels zero, post-commit revocation; no physical output
PASS total frame update deadline with current authorization and timely transactions
PASS 575 frame stage scenarios: normal/wrap, 174 write NACKs, 174 read NACKs, 174 mismatches, 20 initial authorization rejections, 25 mid-transaction revocations, terminal latch, nonzero PWM with zero IREF rejected, stale guard, total deadline, poll gap, clock loss.
PASS integrated full-bank pause, 174 frame matches, diagnostic resume and new sequence; synthetic permissions only
PASS 7 integrated bus scheduling scenarios
PASS 546 off-only GPIO cases: latch/clock/remap combinations, mode, open-drain, pad mismatch, oscillator conflict, unrelated-field preservation; model only
