# A108 vacuum three-key target runtime candidate

Build with `sh build.sh`, test with `sh test.sh` from this directory. Target sources include pinned STM32G030 CMSIS, startup and linker files in the adjacent stm32_shared directory; no network fetch is required.

Actual target main now reads PA0 ADC_IN0 USER_ADC and PA2 active-low KEY_IN every scheduled 10ms, calls vpr_step -> pk_step and vui_step, and records an 11x32-bit (44-byte) volatile debugger snapshot. Even epoch values give a coherent candidate read protocol: read epoch, read fields, read epoch again, accept only matching even values. Epoch samples and timestamps wrap naturally. This is a diagnostic record, not the product display. ELF verification confirms the linked call chain, not MCU execution or timing.

The panel matches A107/A106 electrically: none≈4095, plus≈2048, minus≈2815, both≈1668. Candidate debounce is20ms; first settled keys prime state without a command. Valid ADC key transitions retain the previous run request while settling, so speed adjustment does not inadvertently stop the UI request. Unknown ADC or sample gap>100ms immediately cancels it and requires a new released/pressed power edge after qualification. A fault stops it even during debounce. Four logical levels are1..4; default1 remains an engineering assumption. Qualified increasing four-value fan-duty mapping is still absent.

The original complete ADC/nominal current/VBUS diagnostic and tach accounting stay at100ms. The new USER_ADC-only read does not reset tach edge bookkeeping. Main passes the debounced UI run request into the existing fan policy. Physical ADC calibration, fan profile and limits remain invalid; a request produces NOT_READY/fault-latched and the UI cancels it on its next service. Both target output callbacks and each main pass enforce power disabled and zero PWM. Debugger run_requested is never evidence of fan operation.

Learning resources remain false in target: neither a long hold nor the host-only learning pulse implements suction calibration, a two-minute sequence, saved calibration, restart behavior, a low-suction alarm or display percentage. No display driver is added; no I2C GPIO mode is changed. The host test can inject ready=true only to validate the strict>5s pulse, never to grant target output.

ASan/UBSan tests cover stable four-level operation, bouncing/held keys, invalid/unknown ADC, faults during transitions, gaps, rollover, all65536 classifier inputs, learning pulse/no deferred activation, and the existing fan policy/target lock. No hardware flashing, power-up, timing measurement, MCU register simulation, physical fan or manufacturing acceptance is claimed. Additional10ms ADC acquisition worst-case execution time and sampling stability must be measured on STM32G030 hardware, including faults and concurrent100ms diagnostics.
