# Drill-controller STM32G431CBT6 target image candidate

Run sh 固件/drill_target/build.sh from the engineering-package root. The build uses the pinned ST CMSIS Device G4 v1.2.6 register and system headers, the project minimal reset/vector source, and the existing speed, DRV8316, charge-policy, and charge-register modules. It does not use STM32 HAL.

The reset path now calls ST SystemInit and applies explicit GPIO hard-off levels from the A1 pin map. It drives DRV_RUN_REQ (PA5) low, DRV_SLEEP_N (PC14) low, all six TIM1 phase pins (PA7/PA8/PA9/PA10/PB0/PB1) low as GPIO outputs, and CHARGE_EN_N (PA12) high. Output latches are set before changing the pins to outputs.

TIM1, ADC, SPI2, I2C1, USART3, display, encoder, charger, and motor-control policy remain uninitialized. TIM1 MOE is not set, no watchdog is started, and the image does not enable the DRV8316 or charge path. The linked policies are not called. This is a safe-GPIO startup candidate only.

The FOC current-loop candidate in `../drill_driver/motor_foc.*` is compiled as an isolated Cortex-M4F hard-float object during this build, but is not linked into the safe image. Rotor angle/observer, synchronized ADC sampling, TIM1 update/break sequencing, gains, motor current, thermal limits, and loaded-speed behavior remain unverified.

The electrical levels and pin numbers are taken from the project A1 netlist and controller interface, cross-checked against ST DS12589 Rev 6. Actual reset-to-GPIO transitions, external gate polarity, assembled-board levels, watchdog, break input, PWM, current sensing, motor behavior, charging, and product performance have not been tested on hardware.
