#!/usr/bin/env python3
"""Check the Core1106 RGB666 signal-to-module-pad crosswalk for omissions."""

import csv
from pathlib import Path

HERE = Path(__file__).resolve().parent
CSV_PATH = HERE / "Core1106-RGB666-112pad-pinmap-v0.1.csv"

expected = {
    **{f"RGB_DB{i}": 94 + i for i in range(18)},
    "RGB_DE": 93,
    "RGB_HSYNC": 92,
    "RGB_VSYNC": 91,
    "RGB_CLK": 90,
}

with CSV_PATH.open(newline="", encoding="utf-8-sig") as handle:
    rows = list(csv.DictReader(handle))

signals = [row["panel_signal"] for row in rows]
pads = [int(row["module_pad"]) for row in rows]
assert len(rows) == 22, f"expected 22 RGB666 signals, got {len(rows)}"
assert set(signals) == set(expected), "missing or unexpected signal names"
assert len(signals) == len(set(signals)), "duplicate signal names"
assert len(pads) == len(set(pads)), "duplicate module pads"
assert all(90 <= pad <= 111 for pad in pads), "pad outside RGB signal range"
assert {row["panel_signal"]: int(row["module_pad"]) for row in rows} == expected
assert all(row["io_bank"] == "VCCIO6" for row in rows)

for signal in [f"RGB_DB{i}" for i in range(18)]:
    row = next(row for row in rows if row["panel_signal"] == signal)
    expected_soc_bit = int(signal.removeprefix("RGB_DB"))
    assert row["soc_lcdc_function"] == f"VO_LCDC_D{expected_soc_bit}"

print("PASS: 18 RGB data bits + DE/HSYNC/VSYNC/CLK map uniquely to Core1106 pads 90-111.")
print("PASS: all mapped signals are assigned to the VCCIO6 I/O bank.")
print("NOTE: this checks table consistency only; it does not verify voltage, timing, FPC compatibility, or a physical display.")
