#ifndef DRILL_CLOCK_H
#define DRILL_CLOCK_H
#include "stm32g4xx.h"
#include <stdbool.h>
#define DRILL_CORE_HZ 128000000u
#define DRILL_PLL_CONFIG (RCC_PLLCFGR_PLLSRC_HSI | (3u<<RCC_PLLCFGR_PLLM_Pos) | (64u<<RCC_PLLCFGR_PLLN_Pos) | RCC_PLLCFGR_PLLREN)
/* HSI16 /4 *64 /2. No PLLP/Q output, no HSE (PF1 is nSLEEP). */
static inline bool drill_clock_available(void) {
 return SystemCoreClock==DRILL_CORE_HZ &&
 (RCC->CR&(RCC_CR_HSION|RCC_CR_HSIRDY|RCC_CR_PLLON|RCC_CR_PLLRDY|RCC_CR_HSEON|RCC_CR_HSEBYP))==(RCC_CR_HSION|RCC_CR_HSIRDY|RCC_CR_PLLON|RCC_CR_PLLRDY) &&
 RCC->PLLCFGR==DRILL_PLL_CONFIG &&
 (RCC->CFGR&(RCC_CFGR_SW|RCC_CFGR_SWS|RCC_CFGR_HPRE|RCC_CFGR_PPRE1|RCC_CFGR_PPRE2))==(RCC_CFGR_SW_PLL|RCC_CFGR_SWS_PLL) &&
 (RCC->APB1ENR1&RCC_APB1ENR1_PWREN) && !(RCC->APB1RSTR1&RCC_APB1RSTR1_PWRRST) &&
 (PWR->CR1&(PWR_CR1_VOS|PWR_CR1_LPR))==PWR_CR1_VOS_0 && (PWR->CR5&PWR_CR5_R1MODE) && !(PWR->SR2&PWR_SR2_VOSF) &&
 (FLASH->ACR&FLASH_ACR_LATENCY)==FLASH_ACR_LATENCY_4WS;
}
bool drill_clock_init(void);
#endif
