{
  "version": "v0.23",
  "native_PCB_sha256": "737d69d983ccb9c13a80d317fe0d13f905f8dcec40465f5caf06a20e6aac4f5c",
  "native_netlist_sha256": "ba39fedeff61c8eb09663ebdbf8c3442b12cb7bd6674e115d5d4232b5a787247",
  "selection_sha256": "127c7165c6be23ad890a60620be4d8adb4e2b6c1d6497c8452dbe76ea15b0afb",
  "coverage_csv_sha256": "5df267c4f883427178d11ebc5108211cc04047719d1491b3fae6a8a8cfe3b756",
  "verifier_sha256": "41f02f83c3fc3a75e4f4c6afb2821078dade0cc3e3a67ef4277300ea1f4f4bce",
  "electrical_references": 213,
  "mechanical_only_excluded": [
    "H1",
    "H2",
    "H3",
    "H4"
  ],
  "native_numbered_pad_instances": 619,
  "independent_pin_review_refs": 52,
  "independent_pin_review_pad_instances": 280,
  "independent_pin_review_remaining_refs": 161,
  "geometry_approval": "NOT_COMPLETE",
  "current_work": "Four new core-chip pin reviews plus213-ref coverage ledger; old48 retained against same native hash",
  "scope": "Identity consistency of every reference is NOT an independent213-component pin/geometry/DFM/physical approval",
  "native_ERC_DRC": "INHERITED_V19_NOT_RERUN",
  "physical_tests": "NOT_RUN",
  "manufacturing_release": "HOLD"
}
