Open hardware · Smart pet electronics

Smart litter-box controller.Motion, sensing and control.

An A1 control-board design combining motor drive, precision weighing, sensor interlocks and Wi-Fi connectivity. Explore the circuit architecture, engineering decisions and editable KiCad source.

  • 12 V design input
  • 4-layer PCB
  • STM32G0 + ESP32-C3
  • CERN-OHL-P-2.0
Smart litter-box controller PCB with connector labels and component reference markings

One board. Six connected engineering tasks.

The design separates motor power, low-level weighing signals, local control and wireless communication. Eleven hierarchical schematic sheets keep the power, sensing and interlock paths traceable.

A1 functional architecturePOWERSIGNAL / CONTROL
INPUT POWER & LOGIC RAILS
12 V INPUTFuse + reverse-polarity protectionSMBJ15A transient suppression
PROTECTED BUSMotor and auxiliary branchesSwitched LED / UV outputs
LOGIC SUPPLY2 × TPS54302 buck stagesLocal control and sensor domains
MOTOR POWER & FEEDBACK
12 V MOTOR BUSProtected input branchMotor current path
H-BRIDGEDRV8876Current sense + fault flag
ACTUATORBrushed DC motorDirection-controlled drive

STM32G0 drive commands go to the H-bridge; current-sense and fault signals return to the local controller.

SENSOR INTERLOCKS
INPUTSHall · home · lid · IR · pinchSeparate sensor channels
CONDITIONINGTLV1704 + SN74LVC logicWindow detection and interlock path
LOCAL CONTROLSTM32G030C8T6Sensor state and motion control
PRECISION WEIGHING
BRIDGENominal 350 Ω load cellDifferential sense pair
ANALOG FRONT ENDADS1232 · 24-bit ADCFiltering and reference routing
MEASUREMENTSTM32G0Calibration and reading logic
WIRELESS & AUXILIARY I/O
LOCAL MCUSTM32G0Local sensing and control
RADIO MODULEESP32-C3-WROOM-02-N4Wireless interface
CONNECTORSDisplay UART · AUX I²C5 V display supply; 3.3 V logic

Schematics and copper, from the editable design.

Source-derived previews show how the 12 V motor path and low-level weighing front end connect to the routed PCB.

KiCad A1 motor-driver schematic detail with the DRV8876 H-bridge and 12 V brushed-motor outputs
SCHEMATIC · 06 / MOTORH-bridge drive and current feedbackDRV8876 control, VM supply, motor outputs and IPROPI sensing in one circuit view.
KiCad A1 weighing schematic detail with the ADS1232 24-bit ADC and load-cell bridge inputs
SCHEMATIC · 07 / WEIGHBridge signal conditioningADS1232 input pairs, analog reference, filtering and MCU data lines for a nominal 350 Ω bridge.
A1 KiCad PCB top-copper routing view with tracks, surface components and connector footprints
PCB ROUTING · F.CUComponent placement and top-layer routingExported directly from the A1 KiCad board. The editable source package contains the four-layer PCB and complete copper data.
INPUT & POWER

Protection at the 12 V bus

A 3 A fuse selection, AO4407A reverse-polarity stage and SMBJ15A transient suppressor form the input network. Two TPS54302 buck stages supply the logic domains. Inrush, motor regeneration and fuse coordination drive the protection review.

LOCAL CONTROL & CONNECTIVITY

MCU and Wi-Fi responsibilities

The STM32G030C8T6 handles the local control interface, with a TPS3839 supply supervisor. An ESP32-C3-WROOM-02-N4 module provides the wireless interface. Separate SWD and Wi-Fi programming connections support board bring-up and firmware access.

MOTOR DRIVE

Direction, current and faults

A DRV8876 H-bridge connects to the brushed DC motor. Its current-sense feedback and fault signals give the control architecture inputs for load monitoring and fault handling. Motor current, reversal energy and driver dissipation determine the operating envelope.

WEIGHING

A dedicated bridge front end

The ADS1232 24-bit ADC interfaces with the nominal 350 Ω bridge connection. Input filtering, reference routing, ground return and calibration must preserve a small differential signal beside a switching motor and a radio module.

SENSOR & INTERLOCK LOGIC

Condition signals before motion

Hall, home, lid, infrared and left/right pinch channels are defined separately. TLV1704 comparator stages and SN74LVC logic form the window-detection and hardware-interlock path. Thresholds, cable faults and reset behavior require coordinated hardware and firmware rules.

DISPLAY & AUXILIARY I/O

Interfaces with explicit voltage domains

The display header provides a 5 V supply with 3.3 V UART logic; the auxiliary I²C header uses 3.3 V logic. Switched 12 V LED and optional UV outputs have a 0.2 A design limit per channel. Optional UV operation needs a defined enclosure and interlock requirement.

ConnectorFunctionKey interface details
J1 / J212 V input / motorJ1: VIN_RAW, GND · J2: MOTOR_A, MOTOR_B · JST-VH 3.96 mm family
J3Display / controls6-pin header; +5 V supply, 3.3 V UART logic, reset and user-key signals
J4 / J5Hall / IRSeparate 3-pin inputs with +5 V, GND and a dedicated sensor signal
J6 / J7 / J8 / J10Pinch / home / lidDedicated left/right pinch, home-contact and lid-interlock signals; full pin order in CSV
J9Weight bridge5-pin nominal 350 Ω bridge connection to the ADS1232 front end
J11 / J12UV / LED outputsSwitched 12 V outputs with a 0.2 A design limit per channel
J13 / J14 / J15Aux I²C / SWD / Wi-Fi programming3.3 V logic and reference connections; consult the pin-level CSV before wiring

Signal names follow the A1 schematic. Check the connector orientation, mating part and harness polarity against the target appliance before wiring.

The difficult work happens between subsystems.

Component selection is only one part of the design. The main challenges are the interactions between motion, measurement, interlocks and the mechanical assembly.

01

Motor transients and thermal margin

Stall, start-up, braking and reversal produce different electrical stresses. The driver, bulk capacitance, TVS, fuse and copper paths need one consistent current and energy budget. The routing audit records 0.5 mm motor-output traces and local motor-bus neckdowns of about 0.375–0.401 mm; current and temperature limits must be assessed with the selected motor.

02

Weighing stability beside switching loads

Motor PWM, regulator switching and wireless activity can disturb bridge measurements. The design review therefore considers analog return paths, input symmetry, reference decoupling and measurement timing. Zero tracking, load calibration and filtering belong in the complete weighing strategy.

03

Interlock state transitions

A useful interlock specification covers more than a normal sensor reading: open cables, short circuits, reset, brownout, a stuck input and communication loss all need defined states. Hardware gating, MCU commands and fault recovery must agree on when motion is permitted and how it is stopped.

04

Mechanical and harness compatibility

The A1 outline is 120 × 116 mm, with four mounting holes and a 1.6 mm, four-layer stack-up. Board-edge clearances, connector keying, cable exits, component height and the antenna environment all affect integration. The source makes these design choices inspectable for adaptation to a specific enclosure.

A1 board underside and connector positions

Inspect the circuit. Follow the connections.

The package includes editable KiCad 10 schematics and PCB source, a schematic PDF, a component BOM, connector definitions and machine-readable design audits.

  • 11 functional schematic sheets covering input, power, MCU, sensor loops, comparator windows, interlocks, motor, weighing, Wi-Fi, I/O and test points
  • 202 components and 119 nets in the exported schematic netlist; 543 connected pin mappings checked for round-trip consistency
  • Four copper layers, 2,289 track segments and 319 vias in the routed-board audit
  • 180 BOM rows with manufacturer part numbers, plus source checksums and bilingual project notes
0Reported schematic ERC violations
0Strict PCB DRC violations
0Unconnected PCB items
202 / 119Schematic components / nets

These records contain the KiCad checks behind the figures above. Electrical ratings, dimensional requirements and acceptance limits are set for the target appliance. Component references: DRV8876, ADS1232, TPS54302.

Electronics shaped around the appliance.

The enclosure, rotating mechanism, sensor placement and service access define the controller requirements. Share those interfaces early so the electrical design and mechanical assembly can be reviewed together.

Litter-box controller board with an automatic litter box and cat

CERN-OHL-P-2.0

The original hardware design source is shared under the permissive CERN Open Hardware Licence Version 2. Commercial use and modification are allowed under its terms and notice requirements. The download contains the full licence; see the official licence text.

Source & licence

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