A PCBA test plan should be designed before pilot production. If testing is added after defects appear, the design may lack test points, fixture access, firmware hooks, or clear pass/fail limits. Early test planning reduces field risk and makes production data more useful.
Reference context: acceptance inspection and functional verification answer different questions. IPC describes J-STD-001 as covering soldering processes and materials, and IPC-A-610 as post-assembly acceptance criteria. A product-specific test plan should therefore define functional pass/fail limits, ownership, and data retention rather than treating visual acceptance alone as proof of product behavior. See the engineering editorial and evidence standards for how this guide uses sources and team attribution.
Choose the method first with ICT, FCT, or flying probe. Use this page to write the actual plan: what each station proves, which numeric limits are recorded, and which fields follow the serial number. Method comparison alone lives in the PCBA testing guide.
Illustrative industrial I/O controller — not a customer claim
Example scenario: a 24 V isolated I/O controller for a staffed machine cell. The board mixes SMT and through-hole connectors, eight digital inputs, eight relay or transistor outputs, RS-485, a programmed MCU, and one memory BGA. Failure stops one machine; it is not a safety function. The first buy is 50 pieces for EVT, then about 200 pieces per quarter if the I/O map stays frozen.
This is an illustrative decision pattern for industrial control PCBA. It is not a description of a completed PCBA Partner customer project, measured yield, or quoted NRE.
Failures the plan must catch
AOI can miss several field failures on this class of board. The plan therefore names the failure, the station that should catch it, and the record that proves the check ran:
| Failure that matters | Station that should catch it | What “pass” must include |
|---|---|---|
| Wrong firmware image or MCU blank | Programming + FCT identity check | Filename, version, checksum, and serial in the log |
| Reversed connector or swapped I/O bank | AOI polarity + FCT channel map | Each DI/DO address exercised, not a single “all outputs OK” |
| Open, short, or wrong-value on accessible nets | Flying probe on EVT; ICT later if test points exist | Program revision and fail net ID |
| Hidden BGA joint defect on the memory package | X-ray per the RFQ sample rule | Image or void report tied to the unit or lot |
| Idle current or comms out of window | FCT | Numeric limit with unit, not a green screen |
| Isolation or coating skip where the drawing requires it | Not covered by ICT/FCT unless specified | Separate process evidence; do not imply electrical test proved creepage |
Worked station plan for the example board
| Station | Example limit to record | Retained field |
|---|---|---|
| SPI / AOIEvery SMT lot | Program ID; BGA pads reviewed as their own SPI population | Program revision, fail code |
| X-ray100% of U12 on EVT; sample later if agreed | Signal-ball void and bridge/HIP criteria named in the RFQ | Image or void report, unit or lot ID |
| Flying probeEVT 50 pcs while the revision is still moving | Opens, shorts, selected values on accessible nets | Program revision, fail net |
| ProgrammingEvery unit after the firmware freeze | Image io-ctrl-1.4.2 with checksum recorded | Checksum, station, serial |
| FCTDVT and repeat lots once the I/O map is frozen | 24.0 V ±0.3 V input; idle 85–110 mA; RS-485 ID match; 8 DI / 8 DO | Measured values, firmware, serial, timestamp |
The idle-current window and I/O map above are example placeholders for this scenario. A real RFQ must replace them with the product schematic, loads, and customer limits. Isolation, coating, and environmental qualification stay outside this electrical plan unless the RFQ adds them.
Fixture NRE versus flying-probe time
Do not pick a fixture because it sounds more “production.” Recover the fixture only when the procedure is stable enough to reuse:
- Keep flying probe for the 50-piece EVT if nets are still changing and fixture delay would freeze the wrong revision.
- Authorize an FCT fixture when the connector map, firmware identity check, and numeric limits are frozen and will run on the quarterly 200-piece lots.
- Add ICT only if the layout already exposes test points and the yearly quantity makes bed-of-nails cheaper than probe time. If test points were never designed in, ICT is not a later surprise; it is a layout change.
Ask the quotation to separate fixture NRE, programming, X-ray, flying-probe or ICT time, and FCT cycle time. A single “test included” line hides the plan.
Records that must follow the serial
For a serialized industrial board, agree whether the retained file connects serial number, firmware checksum, station ID, timestamp, PASS/FAIL, measured values, and fail code. Screenshots without those fields cannot support containment. Ownership of the fixture, golden unit, and limit file belongs in the same RFQ note.
Practical takeaway
A high-reliability test plan is a list of failures, stations, numeric limits, and retained fields—not a longer equipment list. Write those four items before the pilot. PCBA PARTNER can quote the stations that the RFQ actually names.